1. Field of the Invention
The present invention relates to a fabrication method of a nonvolatile memory device, more particularly, to a fabrication method for improving characteristics and reliability of the nonvolatile memory device.
2. Discussion of the Related Arts
Generally, an effective cell size of a memory cell relating to an integrity of a nonvolatile memory device such as flash EEPROM (Electrically Erasable Programmable Read Only Memory), EEPROM, etc. is determined by two factors.
One of the two factors is a size of a unit cell, and the other is a structure of a cell array. With respect to the memory cell, the minimum cell structure is a simple stacked gate structure.
As the application of a nonvolatile memory has been extended, research and development of the nonvolatile memory such as a flash EEPROM and a flash memory card has been getting more and more attention.
When the nonvolatile semiconductor memory devices such as flash EEPROM, EEPROM, etc., are used as a mass storage media, the most serious problem is the high cost per bit.
Furthermore, for the chip to be used for portable products, low power consumption is required. In order to lower the cost per bit, lots of research in multi bit cells have been conducted.
The integrity of a conventional nonvolatile memory has a one-to-one corresponding relationship to a number of memory cells. On the other hand, a multi bit cell can enhance, remarkably, the integrity of data storage in an identical chip area by storing data of more than one bit per cell instead of reducing the size of the memory cell.
To implement the above-mentioned multi bit cell, each memory cell should be programmed so as to have more than three threshold voltage levels.
For example, in order to store data of two bits per cell, each cell must be programmed so as to have a threshold voltage of four levels (22=4). The four levels of the threshold voltage correspond to logical states 00,01,10,11, respectively.
The most serious problem in the multi level program is that each threshold voltage level has a statistical deviation of about 0.5V from a nominal value.
Accordingly, when the threshold voltage level is precisely adjusted and therefore the deviation in threshold voltage is decreased, the threshold voltage can be programmed with more levels and the number of bits per cell can be increased. In general, in order to reduce deviation in the threshold voltage level, a programming technique which repeatedly performs a programming operation and a verifying operation is used,
In order to program a nonvolatile memory cell to be at a desired threshold voltage level, a series of voltage pulses is applied to the cell.
In order to verify whether or not the threshold voltage of the cell reaches a desired voltage level, a read operation is performed at a time between two adjacent pulses of the voltage pulses. When the result of the verifying operation indicates that the memory cell has reached the desired threshold voltage level, the programming operation is completed,
According to the above-mentioned technique in which the read and verifying operations are repeatedly performed, it is not easy to reduce the error deviation of the threshold voltage caused by a finite pulse width of the program voltage.
Since an algorithm in which the programming and verifying operations are repeatedly performed is implemented in a circuit, the area for a peripheral circuit is enlarged and the program time for the above-mentioned method becomes long.
FIG. 1A is a cross sectional view showing a structure of a general simple stacked nonvolatile memory device. FIG. 1B is a schematic symbol of a general nonvolatile memory cell.
As shown in FIG. 1A, a floating gate 3 is formed on a p type semiconductor substrate 1 with a tunneling oxide film 2 between the floating gate and the semiconductor substrate. A control gate 5 is formed on the floating gate 3. A dielectric film 4 is formed between the control gate 5 and the floating gate 3.
A n type source region 6a and a n type drain region 6b are formed in a surface of a p type semiconductor substrate 1, and are located at both sides of the floating gate 3. The simple stacked gate nonvolatile memory device having the aforementioned structure has disadvantages as follows: its effective cell size and a coupling constant of the control gate 5 are small, and the coupling constant is reduced as the effective cell size of the nonvolatile memory cell is decreased.
Accordingly, in order to prevent the coupling constant value from being reduced, the dielectric film 4 between the floating gate 3 and the control gate 5 is made of an Oxide Nitride Oxide (ONO) film, but a fabrication process of the ONO film is complicated and requires a high temperature annealing process. As shown in FIG. 1B, each nonvolatile memory cell comprises a floating gate 3, as depicted in FIG. 1A, the control gate 5 for controlling an amount of charges to be supplied to the floating gate 3 for programming, and a field effective transistor for reading (or verifying) the amount of the charges supplied to the floating gate 3.
The field effect transistor comprises a floating gate 3, a source 6a, a drain 6b, and a channel region 7 between the drain 6b and the source 6a. 
A programming operation of the nonvolatile memory cell having the aforementioned structure is performed by the current flowing between the drain 6b and the source 6a when the control gate 5 and the drain 6b are supplied with voltages high enough to cause programming.
The current is compared with a reference current. When the current is equal to or less than the reference current, a programming completion signal is generated.
A conventional fabrication method of a nonvolatile memory device will be described with reference to FIG. 2A to FIG. 2K.
FIG. 2A to FIG. 2K are cross sectional views showing the processes of a fabrication method of a nonvolatile memory device.
As shown in FIG. 2A, an oxide film for separating elements (not shown) is formed on a surface of a p type semiconductor substrate 11 on which a cell region and a peri (or peripheral) region are defined. A cell gate insulation film 12 is formed on an active region of the semiconductor substrate 11.
In this case, the cell gate insulation film 12 is formed on the entire surface of the semiconductor substrate 11 of the cell region and the peri region.
A first polysilicon layer 13 for floating gate is formed on the cell gate insulation film 12. The first polysilicon layer 13 is selectively removed by a photolithography technique and etching process so that a plurality of first floating gates 13a are formed.
As shown in FIG. 25, a first insulation film 14 is formed on the entire surface of the semiconductor substrate 11 including the first floating gate 13a and then is selectively removed by a photolithography technique and an etching process so that a plurality of contact holes are formed. Each of the plurality of contact holes is in one to one correspondence with one of the plurality of first floating gates 13a, and a first portion of each surface of the floating gates 13a is exposed through the corresponding contact hole.
Thereafter, a second polysilicon layer 15 is formed on the semiconductor substrate 11 and at the same time fills the plurality of contact holes.
On the other hand, the first insulation film 14 formed on the peri region of the semiconductor substrate 11 is removed when the contact holes are formed.
As shown in FIG. 2C, a second insulation film 16 for controlling an amount of charges of the floating gate is made of an ONO (Oxide Nitride Oxide) film or CVD insulation film on the second polysilicon layer 15.
As shown in FIG. 2D, a third polysilicon layer 17 for forming a control gate is formed on the second insulation film 16. A cap insulation film is formed on the third polysilicon layer 17 and thereafter selectively removed by a photolithography technique and an etching process so that a plurality of the cap insulation films 18 are formed on the third insulation film 17. Each of the plurality of cap insulation films 18 correspond to only one of the plurality of contact holes.
As shown in FIG. 2E, a first photoresist 19 is deposited on the semiconductor substrate 11 Including the cap insulation film 18 and then is patterned by exposure and development process.
Using the patterned first photoresist 19 and the cap insulation film 18 as a mask, the third polysilicon layer 17 is selectively removed so that a plurality of control gates 17a are formed.
As shown in FIG. 2F, the first photoresist 19 is completely removed. Thereafter, by using the cap insulation film 18 as a mask and performing a blank etch process, the second insulation film 16 and the second polysilicon layer 15 are selectively removed. As a result, a plurality of second floating gates 15a are formed.
In this case, a portion of each of the control gates 17a which is not overlapped with the cap insulation film 18 is selectively removed by the blank etch process and at the same time the second insulation film 16 and the second polysilicon layer 15 which are formed below the control gates 17a are also selectively removed. As a result, the second insulation film 16 has the same width as the control gate 17a and the second floating gate 15 has the same width as the original control gates 17a depicted in FIG. 2E.
In this case, the control gate 17a and the second insulation film 16 which are formed on the peri region of the semiconductor substrate 11 are completely removed from the peri region, but the second polysilicon layer 15 formed on the peri region remains on the peri region.
Thereafter, a third insulation film 20 is formed on the entire surface of the semiconductor substrate 11 including the cap insulation film 18.
As shown in FIG. 2G, a second photoresist 21 is formed on the third insulation film 20 and thereafter is patterned by an exposure and etching process to remain only in the cell region.
Using the patterned second photoresist 21 as a mask, the second polysilicon layer 15, the first polysilicon layer 13 and the cell gate insulation film 12 that have been formed in the peri region are removed.
On the other hand, when the second polysilicon layer 15, the first polysilicon layer 13 and the cell gate insulation film 12 are removed from the peri region, the first polysilicon layer 13 and the second polysilicon layer 15 may remain on the sides of the first insulation film 14 as sidewalls. Therefore, an over-etch process is performed in this case.
As shown in FIG. 2H, by using the second photoresist 21 as a mask, channel ions 22 are implanted in the peri region of the semiconductor substrate 11.
As shown in FIG. 21, the second photoresist 21 is removed. Thereafter, a third photoresist 23 is formed on the semiconductor substrate 11 and then patterned by an exposure and development process to remain only on the peri region of the semiconductor substrate 11.
An etch back process is performed on the entire surface by using the patterned third photoresist 23 as a mask. As the result, a third insulation film sidewall 20a is formed on each side of the cap insulation films 18 and the control gates 17a. 
As shown in FIG. 2J, the third photoresist 23 is removed. Thereafter, by performing an oxidation process on the semiconductor substrate 11, a tunneling insulation film 24 and a peri gate insulation film 25 are formed on the exposed surface of the second floating gate 15a and on the peri region of the semiconductor substrate 11, respectively.
As shown in FIG. 2K, a third polysilicon layer for forming an erasure gate is formed on the semiconductor substrate 11 and then selectively removed by a photolithography and etch process. Therefrom, erasure gates 26a on the cell region and a gate electrode 26b on the peri region are simultaneously formed. The processes for forming a source/drain impurity region and wiring are not illustrated in the drawings.
The above-mentioned conventional fabrication method of the nonvolatile memory device has problems as follows:
First, in order to improve reliability and characteristics of the cell, the gate insulation film is as thin as possible. However, since the semiconductor substrate of the peri region may be damaged when the over etch process is performed to remove the first and second polysilicon layers for floating gate material remaining on the peri region, a thick gate insulation film must be formed for preventing the semiconductor substrate from being damaged.
Second, since the gate insulation film on the peri region and the tunneling insulation film on the cell region are simultaneously formed and therefrom the gate insulation film in the peri region is also changed as the characteristics and thickness of the tunneling insulation film is adjusted to improve characteristics of the cell, the characteristics of the peri elements are not guaranteed.
Third, when the erase gate and the gate electrode are simultaneously formed, it results in a step difference between the peri region and the cell region. Therefore, it is difficult to form a pattern of desired size because a focus difference in a photolithography technique is caused by the step difference.
The present invention is directed to solve the problems of the conventional fabrication method of a nonvolatile memory device described as above.
One object of the present invention is to provide a fabrication method of nonvolatile memory device separately adjusting a thickness of a gate insulation film so as to guarantee reliability and characteristics of the memory cell.
Another object of the present invention is to provide a fabrication method of nonvolatile memory device adjusting a thickness and characteristics of tunneling insulation film in a cell region as well as guaranteeing characteristics of peri elements by forming a tunneling insulation film and a peri gate insulation film by an independent process, respectively.
A further object of the present invention is to provide a fabrication method of nonvolatile memory device improving a process margin of a photolithography technique in a wiring process by forming independently peri gate electrodes and erase gates and then reducing a step difference between the cell region and the peri region as well as improving a focus margin of a photolithography technique.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the fabrication method of nonvolatile memory device according to the present invention comprises the steps of: forming a second conductivity type transistor in a peri region of a first conductivity type semiconductor substrate on which a cell region and said peri region are defined; forming a first insulation film in said peri region of the semiconductor substrate; forming a plurality of first floating gates separated by a predetermined interval on said cell region of said semiconductor substrate with a gate insulation film between the cell region and each of the plurality of first floating gates; forming a second insulation film on the entire surface of said semiconductor substrate so as to have a plurality of contact holes in one to one correspondence to each of said plurality of first floating gates and to expose a portion of surface of the corresponding one of said plurality of first floating gates; forming a plurality of second floating gates, each of the second floating gates formed in one of said plurality of contact holes and on said second insulation film in proximity to the corresponding contact hole; stacking a control gate and a cap insulation film in sequence on a first portion of each surface of said plurality of second floating gates with a third insulation film between the control gate and the portion of the corresponding second floating gate; forming a fourth insulation film sidewall in each side of said plurality of cap insulation films and said plurality of control gates; forming a tunneling gate on an exposed portion of each surface of said plurality of second floating gates; and forming an erase gate on each surface of said plurality of tunneling insulation films and on each region between two adjacent control gates so as to overlap with a first portion of the upper surface of the two adjacent control gates.
Additional features and advantages of the present invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objects and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the accompanying drawings.